OpenAI's first chip is a Broadcom chip, and the interesting number isn't on the box

OpenAI and Broadcom announced Jalapeño on Tuesday, OpenAI's first custom inference accelerator. The press release makes two claims: the chip delivers "performance per watt substantially better than state-of-the-art," and design-to-tape-out took nine months instead of the usual two to three years. Neither claim comes with a number attached. The interesting structural reading is in what the two claims, taken together, imply about where OpenAI thinks its binding constraint is — and whose business model is quietly being rebuilt around that view.

What was actually announced. Jalapeño is an ASIC (application-specific integrated circuit, a chip designed for one workload) built by Broadcom for OpenAI's LLM inference. Inference-only — it does not train models, it runs them. Initial deployment is targeted for end of 2026, scaling through 2027 and 2028, with Microsoft named as a deployment partner. OpenAI VP of Hardware Star Xu will present design principles at a future Hot Chips conference. No process node has been confirmed; Futurum Group's Mike Demler notes the open question of whether this is TSMC N3 or N2.¹²

The performance-per-watt claim is, at this stage, marketing. OpenAI's own release says: "at this early stage, we are not commenting on specific performance metrics."¹ No baseline accelerator is named. No benchmark is given. The structural reading therefore has to be built from the things OpenAI has disclosed elsewhere — particularly the previously stated 10-gigawatt custom-chip power target.

Why 10 GW is the number that matters. OpenAI has said it intends to run enough custom silicon to consume ten gigawatts of power. That is the binding number. Any performance-per-watt improvement Jalapeño delivers is a multiplier on that ten-gigawatt envelope. A twenty per cent efficiency gain means twenty per cent more inference inside the same power and facility footprint, or the same inference at a meaningfully smaller capex bill. This is the inference economics (the cost of running models, not training them) story stated structurally: at frontier-lab scale, the binding constraint has migrated from training compute to inference compute, and from chip count to power draw. Jalapeño is built for that constraint.

The unverified performance claim still tells you something. OpenAI is signalling that it believes the per-token cost curve can be bent at the silicon layer, not just the model layer. If they are right, and we will not know until Hot Chips, or until a third-party teardown, then OpenAI's medium-term margin position improves at current API prices, or it can fund price cuts that squeeze API-dependent competitors. That is the structural bet. The number to wait for is the benchmark Star Xu eventually puts on a conference slide.

This is the Google TPU playbook, run again. Google began its TPU programme through Broadcom around 2016. It took several generations before Google's silicon meaningfully reduced its Nvidia dependence, and even longer before Google brought serious architectural work in-house. OpenAI is at generation one of the same arc, with the same partner. The financial read is in Broadcom's numbers: AI revenue of $12.2 billion in fiscal 2024, guided to $20 billion-plus in fiscal 2025, roughly 64 per cent growth, with the majority coming from custom ASICs sold to Google (TPU), Meta (MTIA), ByteDance, Apple and Microsoft.³ OpenAI joins that roster. Broadcom shares are up about 7x since the end of 2022, which is the market pricing exactly this playbook repeating across every serious AI buyer.

That is the product. Every hyperscaler and frontier lab eventually wants negotiating leverage against Nvidia's pricing power, and Broadcom's custom ASIC services are the most credible route to it short of building a chip team from scratch. The Jalapeño announcement is one more validation of that thesis, and it is why the equity reaction lives more in AVGO than anywhere else.

The vertical integration question, which is also an IP question. "OpenAI's first custom chip" is the framing. The more precise framing is: OpenAI's first chip co-designed with Broadcom, where Broadcom's standard custom ASIC engagements have historically left significant architectural IP with Broadcom. Futurum's Demler flags this directly: "Will OpenAI own the IP, or does Broadcom retain design elements under the partnership structure?"² The answer shapes how much negotiating leverage the Jalapeño programme actually generates. If Broadcom retains the architectural core, OpenAI has traded a Nvidia dependency for a Broadcom dependency — better-priced, probably, but still a dependency. Google's eventual independence came from years of bringing the design work in-house. OpenAI's roadmap on that question is currently undisclosed.

The nine-month tape-out is the more striking signal, and the more qualified one. Greg Brockman on X: "Nine months from chip design to tape-out (vs typical 2-3 years), extensively using OpenAI's own models throughout the process."⁴ Futurum's Demler calls it "the EDA world's Copilot moment" — EDA being electronic design automation, the software toolchain semiconductor engineers use to design chips.²

I would read the nine-month number carefully. Demler's own qualifier, in the same note: "The nine-month tape-out is likely a best-case outcome... enabled by high-level AI assistance in specific steps (verification, place-and-route, timing closure) — not end-to-end autonomous silicon design."² He also raises the scope question directly: an inference-only ASIC is architecturally simpler than a combined training-and-inference chip. Some unknown share of the timeline compression is AI tooling; some is reduced scope. Both numbers are interesting; conflating them inflates the story.

Even with the qualifiers, this is the first publicly disclosed case of an AI lab using its own models to design the silicon that will run those models. The recursive shape of that is real, and it is the kind of toolchain-level acceleration that intelligence-explosion frames predict. The honest version is: AI-assisted EDA compressed specific stages of a constrained design problem, and the compression is large enough to be worth tracking across the next generation of custom silicon programmes. Whether the nine months becomes six on Jalapeño v2, or stretches back toward eighteen on a harder problem, will tell you whether this was tooling or scope.

What to watch.

• Star Xu's Hot Chips presentation, for any disclosed performance-per-watt number against a named baseline. Without it, the headline claim stays marketing.
• TSMC process node (N3 or N2), which sets the credible performance envelope and the second-source risk.
• IP ownership terms between OpenAI and Broadcom, if either side discloses them — the difference between vertical integration and a preferred-customer arrangement.
• Nvidia's response in the 2027 product cycle. The 18-30 month deployment gap is real runway. If Blackwell's successor closes the performance-per-watt gap before Jalapeño reaches material scale, the competitive logic weakens before it is tested.
• Whether the next custom ASIC programme, at OpenAI or anywhere else, replicates the nine-month figure on a harder problem. That is the test of whether chip design timelines have genuinely shifted or whether one favourable case got generalised.

Footnotes